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HD74SSTV16842
11-bit to 22-bit Buffer with SSTL_2 Inputs and Outputs
REJ03D0829-0200 (Previous: ADE-205-602A) Rev.2.00 Apr 07, 2006
Description
The HD74SSTV16842 is a 11-bit to 22-bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2 data (A) inputs.
Features
* Supports SSTL_2 data inputs * Flow through architecture optimizes PCB layout * Ordering Information
Part Name HD74SSTV16842TEL Package Type TSSOP-64 pin Package Code (Previous code) PTSP0064KA-A (TTP-64DV) T Package Abbreviation Taping Abbreviation (Quantity) EL (1,000 pcs / Reel)
Function Table
Input A L H H: L: High level Low level Output Y L H
Rev.2.00 Apr 07, 2006 page 1 of 6
HD74SSTV16842
Pin Arrangement
Y11A 1 Y10A 2 GND 3 Y9A 4 Y8A 5 VDDQ 6 GND 7 Y7A 8 Y6A 9 Y5A 10 GND 11 Y4A 12 Y3A 13 Y2A 14 GND 15 Y1A 16 Y11B 17 VDDQ 18 Y10B 19 Y9B 20 Y8B 21 GND 22 Y7B 23 Y6B 24 Y5B 25 GND 26 VDDQ 27 Y4B 28 Y3B 29 GND 30 Y2B 31 Y1B 32
64 VDDQ 63 GND 62 A11 61 A10 60 VCC 59 VDDQ 58 GND 57 A9 56 A8 55 VDDQ 54 GND 53 A7 52 A6 51 VDDQ 50 GND 49 NC 48 NC 47 VDDQ 46 VCC 45 VREF 44 A5 43 GND 42 VDDQ 41 A4 40 A3 39 GND 38 VDDQ 37 VCC 36 A2 35 A1 34 GND 33 VDDQ
(Top view)
Rev.2.00 Apr 07, 2006 page 2 of 6
HD74SSTV16842
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage *1, 2 Input clamp current Output clamp current Continuous output current VCC, VDDQ or GND current / pin Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: Symbol VCC or VDDQ VI VO IIK IOK IO ICC, IDDQ or IGND PT Tstg Ratings -0.5 to 3.6 -0.5 to VDDQ+0.5 -0.5 to VDDQ+0.5 50 50 50 100 1 -65 to +150 Unit V V V mA mA mA mA W C Conditions
VI < 0 or VI > VCC VO < 0 or VO > VDDQ VO = 0 to VDDQ TSSOP
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This current will flow only when the output is in the high state and VO > VDDQ.
Recommended Operating Conditions
Item Supply voltage Output supply voltage Reference voltage Termination voltage Input voltage AC high level input voltage AC low level input voltage DC high level input voltage DC low level input voltage High level output current Low level output current Input transition rise or fall time Operating temperature Symbol VCC VDDQ VREF VTT VI VIH VIL VIH VIL IOH IOL t / v Ta Min VDDQ 2.3 1.15 VREF-40 mV 0 VREF+310 mV -- VREF+150 mV -- -- -- -- 0 Typ 2.5 2.5 1.25 VREF -- -- -- -- -- -- -- -- -- Max 2.7 2.7 1.35 VREF+40 mV VCC -- VREF-310 mV -- VREF-150 mV -20 20 10 70 Unit V V V V V V V V V mA mA ns/V C Conditions
VREF = 0.5 x VDDQ
A A A A
Logic Diagram
VREF A1
45 16 35 32
Y1A Y1B
To ten other channels
Rev.2.00 Apr 07, 2006 page 3 of 6
HD74SSTV16842
Electrical Characteristics
Item Input diode voltage Output voltage Symbol VCC (V) Min VIK 2.3 -- VOH 2.3 to 2.7 VCC-0.2 2.3 1.95 VOL 2.3 to 2.7 -- 2.3 0 IIN 2.7 -- ICC *2 2.7 -- *2 2.7 -- ICCD Typ -- -- -- -- -- -- -- -- Max -1.2 -- VDDQ 0.2 0.35 5 45 20 Unit V V Test Conditions IIN = -18 mA IOH = -100 A IOH = -16 mA IOL = 100 A IOL = 16 mA VIN = 2.7 V or 0 VIN = VIH(AC) or VIL(AC), IO = 0 VI = VIH(AC) or VIL(AC),
One data input switching at 50% duty cycle.
Input current (All inputs) Quiescent supply current Dynamic operating per each data input Output high *3 Output low *3 rOH - rOL each separate bit *3 Input capacitance Data inputs
A mA A/ data input pF
rOH rOL rO() CIN
2.3 to 2.7 2.3 to 2.7 2.5 2.5 *1
7 7 -- 2.5
-- -- -- --
20 20 4 3.5
IOH = -20 mA IOL = 20 mA IO = 20 mA, Ta = 25C VI = VREF310 mV
Notes: 1. All typical values are at VCC = 2.5 V, Ta = 25C. 2. Total ICC (max) = ICC + {ICCD (Data) x 11} 3. This is effective in the case that it did terminate by resistance. te
Switching Characteristics
VCC = 1.8 0.15 V
Item Propagation delay time *1 Note: Symbol Min VCC = 2.5 0.2 V Typ Max Unit FROM (Input) TO (Output)
1.6 -- 2.8 ns A Y tPLH tPHL 1. This timing relationship is specified into test load (see waveforms - 1) with all of the outputs switching.
Test Circuit
VTT
*2
50 Test point
*1
C L = 30 pF
Notes:
1. CL includes probe and jig capacitance. 2. VTT = VREF = VDDQ x 0.5 3. Input waveform : PRR 10 MHz, Zo = 50 , Input slew rate = 1 V/ns 20% (unless otherwise noted.)
Rev.2.00 Apr 07, 2006 page 4 of 6
HD74SSTV16842 Waveforms
VIH Input VTT tPLH Output VTT tPHL VIL VOH VTT VTT VOL
Rev.2.00 Apr 07, 2006 page 5 of 6
HD74SSTV16842
Package Dimensions
JEITA Package Code P-TSSOP64-6.1x17-0.50 RENESAS Code PTSP0064KA-A Previous Code TTP-64DV MASS[Typ.] 0.47g
*1
D F 33
64
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Terminal cross section ( Ni/Pd/Au plating )
*2
1 Z e
*3
32 bp x M
Reference Dimension in Millimeters Symbol
c
Min
L1
y
A1
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Nom Max 17.0 17.2 6.10
0.00 0.05 0.10 1.20 0.15 0.20 0.25 0.10 0.15 0.20 0 8 7.90 8.10 8.30 0.50 0.08 0.08 0.90 0.4 0.5 0.6 1.0
Rev.2.00 Apr 07, 2006 page 6 of 6
A
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